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TC9204M
Preliminary Data Sheet
4-Port 10/100/1000 Smart Ethernet Switch
Features
Stand Alone Switch On A Chip 4 Ethernet 10/100/1000 ports MII/GMII interface for all ports Four Classes of Service (CoS) selectable for each port and/or checked via IP Header and 802.1Q VLAN Tag Support 4 port-based VLANs Maximum throughput (wire speed), non head-of-line blocking architecture Embedded SSRAM for packet buffer / address table, no external memory required 8K MAC address table 25 MHz crystal input only Each port is configurable to 10 full/half duplex, 100 full/half duplex and 1000 full duplex mode Flow-control ability is able to set for both full and half duplex mode Broadcast throttling Port Mirroring Serial EEPROM Interface, EEPROM is optional MDIO master for PHY configuration / polling 0.18 micron technology 2.0V and 3.3V dual voltage power supply Packaged in PQFP 208 This feature allows improved multimedia applications. support for
The chip embeds IEEE 802.3 MAC functions for each port and these functions support full and half duplex modes for both 10 and 100 Mbits/s data rates and full duplex for 1000 Mbit/s. Each port includes dedicated receive and transmit FIFOs with necessary logic to implement flow control for both full and half duplex modes. TC9204M uses IEEE 802.3x frame based flow control for full duplex and backpressure for half duplex. TC9204M handles an 8K address-lookup table with searching, self-learning, and automatic aging at very high speed and excellent address space coverage. Forwarding rules are implemented according to IEEE 802.1D specifications. Filtering capabilities for bad packets and packets with Reserved Group Address DA are also provided. A port mirror feature, optionally including bad frames, can be used for debugging network problems. The pin configuration interface comprises 40 configurations, which are shared with GMII output pins by latching the configuration data during reset. An external EEPROM device can also be used to configure the TC9204M at power-up. With reference to pin configuration interface, the EEPROM extends the chip's configuration capability with new features and enables a jumper-less configuration mode using a parallel interface for reprogramming. A virtual internal EEPROM mode is also provided to enable the use of the programming interface in the absence of external EEPROM. TC9204M can make effective use by most of its features using only the pin configuration interface. TC9204M includes a physical layer configuration / polling entity, which it is use to configure the phy functions and to monitor the physical layer transceiver's speed, duplex mode, link status and full duplex flow control ability for each port. The chip provides four modes for phy configurations, which these modes include auto-negotiation disable procedure for 10/100 speed modes. The phy configuration information is stored in EEPROM setting.
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General Description
TC9204M is a fully integrated 4-Port 10/100/1000 smart Ethernet switch controller designed for low cost and high performance solutions. The chip embeds necessary SSRAM for packet buffering and MAC address table. It provides MII / GMII interface for all ports. A store-and-forward switching method using a non-blocking architecture is implemented within TC9204M to improve the availability and bandwidth. The chip embeds SSRAM packet buffer, which it supports normal and priority queues for each transmission port. TC9204M provides evolved CoS with four levels of priority. The priority can be checked via layer 2 (802.1Q VLAN Tagging) and/or layer 3 (IP Header TOS bits) packets. Port based priority is also provided to ensure transmission with precedence for all packets incoming from selected port(s).
Confidential. Copyright (c) 2003, IC Plus Corp.
TC9204M
Preliminary Data Sheet
The chip requires a 25 MHz system clock, dual 2.0V and 3.3V power supply and it is packaged in 208 PQFP.
Block Diagram
MDIO interface
EEprom Interface
Configuration Register
From RX MAC
4 GMII/MII RX/TX MAC's
External PHY's
Tx FIFO
Control
Rx FIFO
Queue Management
To TX MAC
Address LoockUp & Resolution Unit
Memory Interface & Arbiter
TC9204M Block Diagram
Internal SSRAM Buffer
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TC9204M
Preliminary Data Sheet
Table Of Contents
Features ..............................................................................................................................................................1 General Description ............................................................................................................................................1 Block Diagram.....................................................................................................................................................2 Table Of Contents ...............................................................................................................................................3 Revision History ..................................................................................................................................................4 Pins Placement...................................................................................................................................................5 1 Pin Listing (PQFP208) ................................................................................................................................6 2 Ethernet Media Access Controller ............................................................................................................14 2.1 Receive MAC ..................................................................................................................... 14 2.2 Transmit MAC .................................................................................................................... 15 3 MAC Address Handling.............................................................................................................................16 4 Queue Management.................................................................................................................................16 5 Classes of Service ....................................................................................................................................17 6 Flow Control ..............................................................................................................................................19 7 Broadcast Throttling ..................................................................................................................................21 8 Port Mirroring.............................................................................................................................................21 9 Physical Layer Configuration / Polling......................................................................................................22 10 EEPROM Interface ...................................................................................................................................23 10.1 Reprogramming the EEPROM for reconfiguration ............................................................ 23 10.2 EEPROM Address Map ..................................................................................................... 24 10.3 Register Description........................................................................................................... 26 10.3.1 Validation Register ................................................................................................ 26 10.3.2 Port [X] Configuration Register ............................................................................. 28 10.3.3 Port [X] IFG Configuration Register ................................................................... 30 10.3.4 Flow Control Register ........................................................................................... 31 10.3.5 Backpressure Time Value Register....................................................................... 33 10.3.6 Flow Control Port Base Address Register ............................................................ 33 10.3.7 Broadcast Configuration Register......................................................................... 34 10.3.8 IP Priority Mapping Register ................................................................................. 35 10.3.9 VLAN Priority Mapping Register ........................................................................... 36 10.3.10 CoS Bandwidth Register....................................................................................... 37 10.3.11 Reserved Register ................................................................................................ 37 CoS Configuration Register .................................................................................. 38 10.3.12 10.3.13 Port Mirroring Register.......................................................................................... 39 General Configuration Register ............................................................................ 40 10.3.14 10.3.15 Port VLAN Enable Register .................................................................................. 41 VLAN [Y] Register................................................................................................. 41 10.3.16 10.4 Writing / Reading PHY management registers via EEPROM interface............................. 42 10.4.1 Data Write Register............................................................................................... 42 10.4.2 Physical Layer Device Address Register .............................................................. 42 10.4.3 Physical Layer's Register Address Register......................................................... 43 10.4.4 IO Status Control Register.................................................................................. 43 10.4.5 Data Read Register .............................................................................................. 44 11 Timing Requirements................................................................................................................................45 11.1 GMII / MII Receive Timing Requirements .......................................................................... 45 11.2 GMII / MII Transmit Timing................................................................................................. 45 11.3 PHY Management (MDIO) Timing ..................................................................................... 46 11.4 EEPROM Timing................................................................................................................ 47 12 Electrical Specifications ............................................................................................................................48 12.1 ABSOLUTE MAXIMUM RATINGS..................................................................................... 48 12.2 RECOMMENDED OPERATING CONDITIONS ................................................................ 48
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TC9204M
Preliminary Data Sheet
12.3 DC CHARACTERISTICS................................................................................................... 48 13 Package Detail ..........................................................................................................................................49
Revision History
Revision # TC9204-DS-R04 TC9204-DS-R05 Change Description 1. Modify "Pin Latched" field in Class of Service section. 2. Correct the register map of "Broadcast Configuration Register" 3. Correct the junction temperature limit.
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TC9204M
Preliminary Data Sheet
Pins Placement
txd45/FcBcstMode txd42/EnPORTPr txd40/priclass40 txd41/priclass41 txd44/FcBcstEn txd47/BcstThrot txd46/OBMTest txen4/RejRDA DisBPBk
FrcFdFc
DisFdFc
DisBkPr
Vdd 2.0
Vdd 2.0
Vdd 3.3
Vdd 3.3
Vss 2.0
Vss 2.0
Vss 3.3
Vss 3.3
Vss 2.0
CarrBp
gtxclk4
208207 206 205204 203 202 201 200199198 197196195 194 193192 191 190 189 188187186 185184183 182 181180 179 178 177 176175174 173172 171 170 169 168 167 166 165164 163162161160 159158 157 NC NC NC NC Vdd 3.3 txd67 txd66 txd65 Vss 3.3 txd64 txd63 txd62 Vdd 3.3 txd61/priclass61 txd60/priclass60 txen6 gtxclk6 Vss 3.3 txer6 txclk6 crs6 col6 rxer6 Vdd 2.0 rxclk6 rxdv6 rxd60 rxd61 rxd62 Vss 2.0 rxd63 rxd64 rxd65 rxd66 rxd67 Vdd 3.3 Vss 3.3 Vdd 2.0 Vss 2.0 Vdd 3.3 Gnd Vss 3.3 Gnd Vdd 3.3 Vss 3.3 NC NC NC NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100101102103104 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 NC NC NC NC NC Gnd Vdd 2.0 Gnd Vss 3.3 VLANPrMap0 Vdd 3.3 VLANPrMAp1 EnVLANPr IPTosMap0 IPTosMap1 EnlPPr rxd27 rxd26 rxd25 rxd24 rxd23 Vss 3.3 rxd22 rxd21 rxd20 rxdv2 rxclk2 Vdd 3.3 rxer2 col2 crs2 txclk2 txer2 Vss 2.0 gtxclk2 txen2 txd20/priclass20 txd21/priclass21 txd22/PriBndw0 Vdd 2.0 txd23/PriBndw1 txd24 txd25 txd26 txd27 reset SysCk Vss 2.0 OvUnLED BcstLED Vdd 2.0 Gtxck
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Testint Vdd 3.3
FullBp
rxclk4
txclk4
rxd47
rxd46
rxd45
rxd44
rxd43
rxd42
rxd41
rxd40
rxdv4
txd43
rxer4
txer4
mdio
mdc
Gnd
Gnd
crs4
col4
Sda txd07
NC
NC
NC
NC
NC
Scl txd06
TC9204M
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
txd05
Vss 3.3
txd04
txd03
txd02
Vdd 3.3
txd01/priclass01
txd00/priclass00
txen0
gtxclk0
Vss 3.3
txer0
txclk0
crs0
col0
rxer0
Vdd 2.0
rxclk0
rxdv0
rxd00
rxd01
rxd02
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Vss 2.0
rxd03
rxd04
rxd05
rxd06
rxd07
Vdd 3.3
Vss 3.3
Vdd 2.0
Vss 2.0
Vdd 3.3
Gnd
Vss 3.3
Gnd
Vdd 3.3
SelSck
NC
NC
NC
NC
NC
NC
NC
NC
July 29, 2003 TC9204M-DS-R05
NC
NC
NC
TC9204M
Preliminary Data Sheet
1
I Is Ipd I/O I/Opd No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Pin Listing (PQFP208)
digital input schmitt trigger digital input digital input with internal pull down digital bi-directional digital bi-directional with internal pull down Pin label NC NC NC NC Vdd 3.3 Txd67 Txd66 Txd65 Vss 3.3 Txd64 Txd63 Txd62 Vdd 3.3 Txd61 priclass61 Txd60 priclass60 Type NA NA NA NA P O O O G O O O P I/Opd I/Opu I/Opu O P G digital bi-directional with internal pull up digital output power ground
16 17 18 19 20 21 22 23 24 25 26 27 28
Txen6 Gtxclk6 Vss 3.3 Txer6 Txclk6 Crs6 Col6 Rxer6 Vdd 2.0 Rxclk6 Rxdv6 Rxd60 Rxd61
O O G I/Opd I Is Is Is P I Is Is Is
Description Reserved for future use Reserved for future use Reserved for future use Reserved for future use Digital +3.3V power supply for I/O GMII transmit data - bits 7 GMII transmit data - bits 6 GMII transmit data - bits 5 Digital ground for I/O GMII transmit data - bits 4 GMII/MII transmit data - bits 3 GMII/MII transmit data - bits 2 Digital +3.3V power supply for I/O GMII/MII transmit data - bit 1 Priority class - most significant bit. GMII/MII transmit data - least significant bit Priority class - least significant bit. Sets priority level per port basis. PriClass[6] - '00' - port 6 low priority PriClass[6] - '01' - port 6 has normal priority PriClass[6] - '10' - port 6 has high priority PriClass[6] - '11' - port 6 has very high priority PriClass[6] is latched on reset GMII/MII transmit enable GMII transmit clock Digital ground for I/O Transmit Error MII transmit clock MII carrier sense indication MII collision indication Receive Error Digital +2.0V power supply for core MII receive clock GMII/MII data valid GMII receive data - least significant nibble. MII receive data GMII receive data - least significant nibble. MII receive data
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TC9204M
Preliminary Data Sheet
Pin Listing (continued)
No. 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Pin label Rxd62 Vss 2.0 Rxd63 Rxd64 Rxd65 Rxd66 Rxd67 Vdd 3.3 Vss 3.3 Vdd 2.0 Vss 2.0 Vdd 3.3 Gnd Vss 3.3 Gnd Vdd 3.3 Vss 3.3 NC NC NC NC NC NC NC Vdd 3.3 Txd07 Txd06 Txd05 Vss 3.3 Txd04 Txd03 Txd02 Vdd 3.3 Txd01 Priclass01 Txd00 Priclass00 Type Description Is GMII receive data - least significant nibble. MII receive data G Digital ground for core Is GMII receive data - least significant nibble. MII receive data Is GMII receive data - most significant nibble Is GMII receive data - most significant nibble Is GMII receive data - most significant nibble Is GMII receive data - most significant nibble P Digital +3.3V power supply for I/O G Digital ground for I/O P Digital +2.0V power supply for core G Digital ground for core P Digital +3.3V power supply for I/O I G Digital ground for I/O I P Digital +3.3V power supply for I/O G Digital ground for I/O NA Reserved for future use NA Reserved for future use NA Reserved for future use NA Reserved for future use NA Reserved for future use NA Reserved for future use NA Reserved for future use P Digital +3.3V power supply for I/O O GMII transmit data - bits 7 O GMII transmit data - bits 6 O GMII transmit data - bits 5 G Digital ground for I/O O GMII transmit data - bits 4 O GMII/MII transmit data - bits 3 O GMII/MII transmit data - bits 2 P Digital +3.3V power supply for I/O I/Opd GMII/MII transmit data - bit 1 Priority class - most significant bit. I/Opu GMII/MII transmit data - least significant bit Priority class - least significant bit. Sets priority level per port basis. PriClass[0] - `00' - port 0 has low priority PriClass[0] - `01' - port 0 has normal priority PriClass[0] - `10' - port 0 has high priority PriClass[0] - `11' - port 0 has very high priority PriClass[0] is latched on reset
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Confidential. Copyright (c) 2003, IC Plus Corp.
TC9204M
Preliminary Data Sheet
Pin Listing (continued)
No. 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pin label Txen0 Gtxclk0 Vss 3.3 Txer0 Txclk0 Crs0 Col0 Rxer0 Vdd 2.0 Rxclk0 Rxdv0 Rxd00 Rxd01 Rxd02 Vss 2.0 Rxd03 Rxd04 Rxd05 Rxd06 Rxd07 Vdd 3.3 Vss 3.3 Vdd 2.0 Vss 2.0 Vdd 3.3 Gnd Vss 3.3 Gnd Vdd 3.3 SelSck NC NC NC NC NC NC NC Type O O G I/Opd I Is Is Is P I Is Is Is Is G Is Is Is Is Is P G P G P I G I P Is NA NA NA NA NA NA NA Description GMII/MII transmit enable GMII transmit clock Digital ground for I/O Transmit Error MII transmit clock MII carrier sense indication MII collision indication Receive Error Digital +2.0V power supply for core MII receive clock GMII/MII data valid GMII receive data - least significant nibble. MII receive data GMII receive data - least significant nibble. MII receive data GMII receive data - least significant nibble. MII receive data Digital ground for core GMII receive data - least significant nibble. MII receive data GMII receive data - most significant nibble GMII receive data - most significant nibble GMII receive data - most significant nibble GMII receive data - most significant nibble Digital +3.3V power supply for I/O Digital ground for I/O Digital +2.0V power supply for core Digital ground for core Digital +3.3V power supply for I/O Digital ground for I/O Digital +3.3V power supply for I/O Selects the source for the system clock. Selsck - `1' - sysck is driven by a 25Mhz external clock. Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use
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TC9204M
Preliminary Data Sheet
Pin Listing (continued)
No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 Pin label NC NC NC NC Gtxck Vdd 2.0 BcstLED OvUnLED Vss 2.0 Sysck Reset Txd27 Txd26 Txd25 Txd24 Txd23 PriBndw1 Vdd 2.0 Txd22 PriBndw0 Type NA NA NA NA I P I/Opd O G I Ipus I/Opd I/Opd I/Opd O I/Opd Description Reserved for future use Reserved for future use Reserved for future use Reserved for future use The 125Mhz reference clock for 1000Mbps operating mode. This clock is used as a reference clock for the GMII transmission clock for every port. Digital +2.0V power supply for core The led can signal either filtering of broadcast frames. Also the led remains lit if the POST test fails, which indicates a faulty chip. The led is lit whenever a unicast packets overflow condition is reached and some frames are dropped by the buffer management engine. Digital ground for core The 25Mhz system clock. General reset. Active Low. GMII transmit data - most significant bit GMII transmit data - bit 6 GMII transmit data - bit 5 GMII transmit data - bit 4 GMII/MII transmit data - bit 3 Priority bandwidth configuration pins. PriBndw(1)is latched on reset Digital +2.0V power supply for core GMII/MII transmit data - bit 2 Priority bandwidth configuration pins. These configuration pins allow the bandwidth percentage assigned to a priority packet queue to be modified to certain hardwired levels. PriBndw chooses between 4 hardwired spreading percentage schemes among the 4 priority queues of each port. PriBndw(0)is latched on reset GMII/MII transmit data - bit 1 PriClass[2] is latched on reset Priority class - most significant bit. GMII/MII transmit data - least significant bit Priority class - least significant bit. Sets priority level per port basis. PriClass[2] - '00' - port 2 low priority PriClass[2] - '01' - port 2 has normal priority PriClass[2] - '10' - port 2 has high priority PriClass[2] - '11' - port 2 has very high priority PriClass[2] is latched on reset GMII/MII transmit enable GMII transmit clock Digital ground for core Transmit Error MII transmit clock MII carrier sense indication
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117 118
P I/Opu
119
Txd21 priclass21 Txd20 priclass20
I/Opd
120
I/Opu
121 122 123 124 125 126
Txen2 Gtxclk2 Vss 2.0 Txer2 Txclk2 Crs2
O O G I/Opd I Is
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TC9204M
Preliminary Data Sheet
Pin Listing (continued)
No. 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 Pin label Col2 Rxer2 Vdd 3.3 Rxclk2 Rxdv2 Rxd20 Rxd21 Rxd22 Vss 3.3 Rxd23 Rxd24 Rxd25 Rxd26 Rxd27 EnlPPr Type Is Is P I Is Is Is Is G Is Is Is Is Is I/Opd Description MII collision indication Receive Error Digital +3.3V power supply for I/O MII receive clock GMII/MII data valid GMII receive data - least significant nibble. MII receive data GMII receive data - least significant nibble. MII receive data GMII receive data - least significant nibble. MII receive data Digital ground for I/O GMII receive data - least significant nibble. MII receive data GMII receive data - most significant nibble GMII receive data - most significant nibble GMII receive data - most significant nibble GMII receive data - most significant nibble Enables IP prioritization. CoS resolution will consider TOS Precedence bits from IP Header. `1' - IP priority will be taken into consideration `0' - IP priority will be neglected EnIPPr is latched on reset IP type of service mapping - the most significant bit IPTosMap(1) is latched on reset IP type of service mapping - the least significant bit. This configuration chooses between 4 hard-wired mapping schemes for the associations of IP priority within the received packet and one of the 4 priority levels set by PriClass. The resolution function is used for the final priority class if the receiving port already has a priority level assigned by PriClass configuration, or the VLAN prioritization is active. IPTosMap(0) is latched on reset. Enables VLAN prioritization. CoS resolution will consider user priority bits (TCI field) from 802.1Q VLAN Tag Header. `1' - VLAN priority will be taken into consideration `0' - VLAN priority will be neglected EnVLANPr is latched on reset VLAN priority mapping VLANPrMap(1)is latched on reset. Digital +3.3V power supply for I/O
142 143
IPTosMap1 IPTosMap0
I/Opd I/Opu
144
EnVLANPr
I/Opu
145 146
VLANPrMap1 Vdd 3.3
I/Opu P
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Preliminary Data Sheet
Pin Listing (continued)
No. 147 Pin label VLANPrMap0 Type Description I/Opu VLAN priority mapping This configuration chooses between 4 hard-wired mapping schemes for the associations of VLAN priority within the received packet and one of the 4 priority levels set by PriClass. The resolution function is used for the final priority class if the receiving port already has a priority level assigned by PriClass configuration, or the VLAN prioritization is active. VLANPrMap(0)is latched on reset. G Digital ground for I/O I P Digital +2.0V power supply for core I NA Reserved for future use NA Reserved for future use NA Reserved for future use NA Reserved for future use NA Reserved for future use I/Opd GMII transmit data - bit 7 Enables broadcast throttling. '1' - Enable '0' - Disable BcstThrot is latched on reset. I/Opd GMII transmit data - bit 6 I/Opd GMII transmit data - bit 5 This pin changes the flow control threshold's behaviour if pin 160 is set to logic 1 (It enables broadcast function). '1' - only the flow control threshold on the broadcast queue is considered '0' - flow control thresholds associated to each source port originating the broadcast frames are considered FCBcstMode is latched on reset. I/Opd GMII transmit data - bit 4 Enables/disables flow control for broadcast packets. '1' - enabled '0' - disabled FcBcstEn is latched on reset. I/Opd GMII/MII transmit data - bit 3 G Digital ground for core I/Opd GMII/MII transmit data - bit 2 I/Opd GMII/MII transmit data - bit 1 Priority class - most significant bit. PriClass[4] is latched on reset.
148 149 150 151 152 153 154 155 156 157
Vss 3.3 Gnd Vdd 2.0 Gnd NC NC NC NC NC Txd47 BcstThrot
158 159
Txd46 Txd45 FcBcstMode
160
Txd44 FcBcstEn
161 162 163 164
Txd43 Vss 2.0 Txd42 Txd41 Priclass41
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Preliminary Data Sheet
Pin Listing (continued)
No. 165 Pin label Txd40 Priclass40 Type Description I/Opd GMII/MII transmit data - least significant bit Priority class - least significant bit. Sets priority level per port basis. PriClass[4] - '00' - port 4 low priority PriClass[4] - '01' - port 4 has normal priority PriClass[4] - '10' - port 4 has high priority PriClass[4] - '11' - port 4 has very high priority PriClass[4] is latched on reset I/Opd GMII/MII transmit enable If this pin is set to '1' then all frames with 802.1D Reserved Group Address or 802.3x Full Duplex PAUSE operation DA will be filtered out. This setting is provided for testing purposes only and it is recommended to set high during normal operation. RejRDA is latched on reset. O GMII transmit clock P Digital +3.3V power supply for I/O I/Opd Transmit Error I MII transmit clock Is MII carrier sense indication Is MII collision indication Is Receive Error G Digital ground for I/O I MII receive clock Is GMII/MII data valid Is GMII receive data - least significant nibble. MII receive data Is GMII receive data - least significant nibble. MII receive data Is GMII receive data - least significant nibble. MII receive data Is GMII receive data - least significant nibble. MII receive data Is GMII receive data - most significant nibble Is GMII receive data - most significant nibble Is GMII receive data - most significant nibble Is GMII receive data - most significant nibble P Digital +3.3V power supply for I/O I/Opd During the normal operation, the backpressure process is executed until flow control condition disappears or until the time limit for backpressure is reached. The backpressure time limit is based in the EEPROM's BPTimeValue register. When this configuration is `0' the backpressure process will also be limited from exceeding 28-consecutive collisions. The default value (28) can be changed in the EEPROM settings. FullBp is latched upon reset
166
Txen4 RejRDA
167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186
gtxclk4 Vdd 3.3 Txer4 Txclk4 Crs4 Col4 Rxer4 Vss 3.3 Rxclk4 Rxdv4 Rxd40 Rxd41 Rxd42 Rxd43 Rxd44 Rxd45 Rxd46 Rxd47 Vdd 3.3 FullBp
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Preliminary Data Sheet
Pin Listing (continued)
No. 187 Pin label CarrBp Type Description I/Opd Enable / disable carrier based backpressure for half -duplex mode. '1' - Carrier based backpressure `0' - Collision based backpressure. CarrBp is latched on reset I/Opd Setting this pin to `1' will disable backpressure procedure for all half duplex ports. DisBkPr is latched upon reset. I/Opd Setting this bit to `1' will force flow control execution for 10/100Mbps, no matter the auto negotiation result. FrcFdFc is latched upon reset. G Digital ground for I/O I/Opd Setting this bit to '1' will disable flow-control for full-duplex mode (transmission of pause frames). DisFdFc is latched upon reset. I/Opd Enable / disable backoff during backpressure. '1' - No backoff executed. Another collision will be forced again after one minimum IFG time following previous collision if carrier sense is observed. '0' - The MAC randomly chooses between 0 and 1 slot times of backoff. DisBkBp is latched during the reset operation. P Digital +2.0V power supply for core I G Digital ground for core I NA Reserved for future use NA Reserved for future use NA Reserved for future use NA Reserved for future use P Digital +2.0V power supply for core O MDIO Clock. I/Opu MDIO Data. G Digital ground for core I/Opu EEPROM's serial clock. I/Opu EEPROM's serial data. I/Opd TestInt - '0' - switch normal mode(default) TestInt -'1' - internal memory test mode.
188 189 190 191 192
DisBkPr NC FrcFdFc Vss 3.3 DisFdFc
193
DisBPBk
194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
Vdd 2.0 Gnd Vss 2.0 Gnd NC NC NC NC Vdd 2.0 mdc mdio Vss 2.0 Scl Sda Testint
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Preliminary Data Sheet
2 Ethernet Media Access Controller
The TC9204M's Ethernet Media Access Controller (MAC) contains IEEE 802.3 MAC functions for 4 Ports. It is able to operate in 10/100/1000 full duplex and 10/100 half duplex modes for all ports. Each port has its dedicated receive and transmit FIFO with necessary logic to implement flow control for both duplex modes. The MAC functions are specially designed for high speed and flexible interfacing.
2.1
Receive MAC
When a frame is received from the Ethernet media through the MII interface, it is then stored in a dedicated receive FIFO. This FIFO acts as a temporary buffer between the Receive MAC section and switch core interface. The Receive MAC layer extracts the valid ethernet information by stripping off the preamble sequence and SFD of the received frame, which the frame was acquired from the PHY layer via either GMII or MII interface. The Receive MAC then sends packets with valid information to the receive FIFO. TC9204M determines the validity of each received packet by checking the CRC and packet length. The bad packets will be dropped either by the MAC or by the queue manager. Oversized packets are truncated to 1536 bytes and marked as erroneous packets. Undersized packets are removed from the receive FIFO without being reported to the switch interface. Therefore the FIFO space held by undersized packets will be removed automatically. In Full Duplex mode the Receive MAC can identify any received frame as a flow control frame having a valid CRC. It will load its internal pause counter with the `pause quanta' value extracted from the incoming frame. The flow control frame will be rejected after the pausing period has been acquired. After the pausing period has obtained from the flow control frame, the flow control mechanism inside TC9204M will set a decremental timer in the pause counter according to the value of the pausing period. A non-zero value sets in the pause counter will issue the Receive MAC to XOFF (Transmit Stop) the Transmit MAC. The pause counter will decrement the `pause quanta' value after each slot time until it reaches zero. If the pause quanta value is equal to zero the flow control mechanism will XON (Transmit Enable) the Transmit MAC. If a frame transmission is in progress when the PAUSE frame is received, the transmission is allowed to complete for the current transmitting frame but the transmission for the next frame(s) will hold until the Receive MAC generates an XON command. The pause time will begin at the end of current transmission or start immediately if no transmission is in the medium when the PAUSE frame is received. If a pause command is received while the transmitter is already in pause, the new pause time indicated by the new Flow Control frame will be loaded into the pause register. The MAC is also able to reject frames containing IEEE 802.1D Reserved Group Destination Addresses and frames with Mac Control Type (Type 88-08) if selected through configuration settings. When the receive FIFO is full and additional data are still incoming from the MAC, then the overrun condition occurs and the frame is dropped. If the system clock frequency is not lower than the recommended value this condition will never occur.
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2.2 Transmit MAC
The Transmit MAC section assembles the MAC frames stored in the transmit FIFO and controls their transmission onto the media via external PHY entities. It appends the standard preamble and start of frame delimiter to the transmitted packets. The MAC also controls the interframe gap time during transmission, maintaining for default the standard minimum interframe gap of 96-bit time. This value can be changed in the EEPROM register setting. For Half Duplex mode the Transmit MAC meets CSMA/CD IEEE 802.3 requirements. The FIFO logic manages frame retransmission for early collision conditions or discards the frame if late collision occurs. It also follows the truncated binary exponential backoff algorithm, collision and jamming procedures. The transmit FIFO stores the packets which are ready for transmission in the main memory queues. If there is no packet ready in the transmit FIFO before the current packet completes its transmission, an underrun condition has occurred and the mechanism will generate a signal to indicate FIFO underrun event, but if the switch core transfers the rest of the packet(s) into the FIFO, the Transmit MAC will safely discard it without affecting the next packet. Underrun conditions never occur if the system is operating at the recommended clock frequency or higher. For full duplex mode TC9204M implements the flow control algorithm according to the IEEE 802.3x standard, using the XON/XOFF method. Full duplex flow control can be configured automatically, by auto-negotiation result, or manually, pin configuration and/or EEPROM settings, to enable/disable the function. The TC9204M executes backpressure algorithm for half duplex flow control supporting both collision based and carrier based backpressure. Both modes are based on carrier sense forced collisions and an aggressive backoff algorithm. The forced consecutive collisions generated for flow control purposes can be limited to a maximum of 28 collisions if this option is selected. This feature helps to avoid HUB partitioning in heavy traffic. The number of collisions can be adjusted in EEPROM settings. MAC Block Diagram
Rx Data (64) T e Value (16) im FC Insert T Data (64) x
System Interface
Rx FIFO
Flow Control
Tx FIFO
Fifo Control Logic
Rx MAC
Tx MAC
MAC
RMII Rx Data (2)
RMII T Data (2) x
RMII
PHY Layer
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3 MAC Address Handling
After the frames are recovered from MAC FIFOs they are transferred to the queue management entity. Prior to this transfer the DA and SA are extracted from each frame and passed to MAC Address Lookup Table and Resolution Engine (ALR). The Lookup engine uses a proprietary hashing algorithm to access its 8K address table. The engine will update its table with each SA, if it is found to be unknown or migrated. Then it will update the source port and aging information along with the new address. This learning process will be executed for all addresses except for multicast SA frames (bit 40 is `1'). For stored addresses, aging function is executed according to the time intervals set in the EEPROM registers. Default aging time is 600 seconds. TC9024M also provide option to disable the aging mechanism, please refer to the EEPROM Register in section 15.3.14 for more details. Destination address is also analyzed in order to make forwarding decisions. If the destination address is a broadcast or multicast address, the frame will flood to all ports except its originated port (source port). If only some ports are allow to send those frame(s) with broadcast or multicast address(es), the destination ports will search the for the port(s) with correct address(s) in the MAC address table. If the address is found to be unknown, the frame will be also flooded to every port, otherwise frame(s) will be forwarded to the legitimate port(s) only. TC9204M will filter following frames: Erroneous frames. This includes : - frames with CRC error; - undersized frames; - oversized frames; - frames that presents alignment error (this doesn't include frames with dribble bits). 802.3x pause frames. These frames will be filtered after executing appropriate flow control actions; Frames with 802.3x full duplex flow control PAUSE operation destination address. These frames are not recognized as pause frames if the MAC type and subtype does not match the "88080001"H value; Frames with 802.1D Reserved Group Address destination address; Frames with MAC Control Type (8808); Local frames. If the port found to correspond to destination address matches the source port, then the frame is considered to be local and discarded.
4
Queue Management
TC9204M operates in a store and forward mode implementing efficient switching method that minimizes the overall latency. The queue manager uses the first in first out forwarding mode, which guarantees to maintain frame order. Congestion control is implemented within TC9204M, which will eliminate head-of-line blocking conditions. The switch embeds a 2 Mbit SSRAM as a central frame buffer pool, which is divided into 208 byte buffers to increase memory utilization efficiency. Normal and priority transmission queues are implemented within TC9204M for each port. All available frame buffers are shared between all transmission queues and each queue can fully extend to all buffers. Still memory resource utilization is limited on receive port basis. Evolved flow control and frame filtering mechanisms are implemented based on source, transmit and global memory load to maximize performance and minimize packet loss.
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5 Classes of Service
TC9204M implements advanced Class of Service (CoS), supporting both traffic priority and delay bound features. It provides four classes of service: class 0 (low), class 1 (normal), class 2 (high) and class 3 (very high). Each class of service has its dedicated transmission queue for each port. The frames assign with higher service class will arrive sooner at the destination. Frames in the class 0 priority queue get the lowest transmission bandwidth percentage, while frames in the class 3 priority queues get the highest bandwidth percentage. The bandwidth percentage depends on two elements: CoS bandwidth weights, and The corresponding class of all non-empty queues for the respective port. The CoS weights can be set by using PriBndw [1:0] shared configuration pins or by setting the EEPROM Registers. While the pins provide only four predefined hardwired combinations for the transmission bandwidth percentage allocation among the queues, the EEPROM gives more flexibility over this configuration. When EEPROM is not present, transmission bandwidth percentage distribution among the queues for the case when all the queues are loaded can be seen in the table below: EEPROM is not present Transmission Bandwidth Percentage Class 0 Priority Class 1 Priority Class 2 Priority (lowest) 7% 13% 27% 3% 14% 27% 2% 8% 30% 3% 5% 10%
PriBndw[1:0] 00 01 10 11
Class 3 Priority (highest) 53% 56% 60% 82%
The percentage refers to the port's bandwidth, which is determined by the current operating speed. Those values are the guaranteed minimum ones and the transmission bandwidth percentage cannot drop below specified value under any circumstance. If EEPROM is used, the user has more flexible adjustment of bandwidth weights to choose from the EEPROM register. A special early packet dropping mechanism is also implemented to offer more protection against overflow conditions for priority packets. If the global memory load exceeds an overflow threshold, then all class 0 priority packets will be dropped from the source port(s) in order to save space for the higher priority packets. This will minimize the probability of packet loss in priority flows for senders that are not flow control capable. The CoS mechanism supports multiple prioritization sources: 802.1Q VLAN Tag Header (layer 2), IP Header TOS bits (layer 3) and/or port based CoS. For IP and VLAN sources a mapping is executed between the values of the fields extracted from each frame and one of the four CoS provided by TC9204M. This mapping can be adjusted by using IPTosMap [1:0] and VLANPrMap [1:0] shared configuration pins or the EEPROM settings. While the pins provide just four predefined hard-wired mapping schemes, the EEPROM gives a custom explicit mapping. Under some circumstances, one or more mechanisms can be actived at same time (VLAN, IP and/or port based). In this case there is a resolution function that resolves the CoS for each incoming frame. When EEPROM is not present and IP and/or VLAN prioritizations are enabled, the corresponding headers of each incoming frames are parsed. The frame will be assigned the CoS corresponding to the first header parsed that found valid. When both above prioritizations are enabled the search order is
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determined by EEPROM configuration (default is IP). If no header is found or corresponding prioritizations are disabled then port based prioritization is executed. When EEPROM is present an additional method of prioritization is available. This method consists of selecting the highest service class from all classes corresponding to the enabled prioritization sources (IP, VLAN and port based). For both methods, when no prioritization source is available the default CoS is used (default is normal priority - CoS1 but it can be also changed by EEPROM configuration). The CoS features can be configured by adjusting shared configuration pins and/or programming EEPROM Register settings. VLAN prioritization can be enabled by EnVLPr shared configuration pin or by EEPROM register settings, while EnIPPr shared configuration pin or the EEPROM Register settings can enable IP prioritization. The shared configuration pins are sampled during reset. The per-port basis CoS can be set using PriClass [x][1:0] shared configuration pins or configuring EEPROM registers, where x stands for port number. The port-based prioritization can be disabled from EEPROM settings only. Pins Latched Description TxDataX_[1:0] Set the priority class per port basis '00' - the port has class 0 priority(lowest priority) '01' - the port has class 1 priority '10' - the port has class 2 priority '11' - the port has class 3 priority(highest priority) Enable/disable IP prioritization EnIPPr `0' - IP priority within the received packet (if exists) is ignored `1' - IP priority within the received packet (if exists) is considered Enable/disable VLAN prioritization EnVLPr `0' - VLAN priority within the received packet (if exists) is ignored `1' - VLAN priority within the received packet (if exists) is considered Selects one of four mappings for the 8 level precedence extracted IPTosMap[1:0] from frame's IP header to the 4 CoS offered by TC9204M (C0, C1, C2, C3 - class 0, 1, 2, 3 of service) Designated priority class IPTosMap[1:0] 0 1 2 3 4 5 6 7 C0 C0 C1 C1 C2 C2 C3 C3 00 C1 C2 C2 C2 C3 C3 C3 C3 01 C1 C1 C2 C2 C2 C3 C3 C3 10 C0 C1 C1 C2 C2 C3 C3 C3 11 Selects one of four mappings for the 8 level user_priority extracted VLANPrMap[1:0] from the frame's VLAN Tag to the 4 level priority offered by TC9204M (C0, C1, C2, C3 - class 0, 1, 2, 3 of service) Designated priority class VLANPrMap[1:0] 0 1 2 3 4 5 6 7 C0 C0 C1 C1 C2 C2 C3 C3 00 C1 C0 C0 C1 C2 C2 C3 C3 01 C0 C0 C0 C1 C1 C2 C3 C3 10 C2 C0 C1 C2 C3 C3 C3 C3 11 Configuration PriClass[x][1:0]
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6 Flow Control
Whenever the memory load exceeds preset thresholds, flow control commands are issued by the traffic management entity to the transmit MACs to prevent overflow conditions occurred. The overrun conditions are either locally or globally triggered, depending on the traffic management entity configuration. Transmit MAC executed those flow control commands depending on the duplex mode status. TC9204M executes backpressure for half duplex operation mode and it is IEEE 802.3x compliant for full duplex operation mode. In special conditions forward-pressure is also executed to eliminate packet loss. For full duplex operation mode, TC9204M applies the XON/XOFF method using IEEE 802.3x PAUSE frames. When a flow control command is internally generated, the transmit MAC inserts a pause frame immediately or after the current transmission ends. On the receiving side, if a flow control frame is received, the transmit MAC will stop transmission for a number of slot times, where the pausing time was extracted from the received pause frame. The flow control function of the receiving side is always operational unless is specifically disabled by EEPROM on a per port basis (if no EEPROM is present the receive side flow-control is always operational), while transmission of the pause frames obeys the auto negotiation result. TC9204M recognizes flow control frames from the incoming frames and these frames should also have a valid CRC. The IEEE 802.3x PAUSE operation reserves destination address, MAC control type and PAUSE opcode (88-08-00-01). The chip filters all frames having PAUSE operation reserved DA disregarding the other fields. If enabled, direct flow control addressing can be executed. This implies inserting the port address as SA in each flow control frame generated by TC9204M and recognizing as flow control all received frames with the port's address as DA, MAC control type and PAUSE opcode. After recognizing and executing appropriate flow control actions these frames will be also filtered. The port address is obtained by adding the port's number to the base address contained within EEPROM. When no EEPROM is present and DisFdFC shared configuration pin is configured to high state, the switch will inhibit its ability to send flow control packets on all ports while preserving its ability to receive and act upon the incoming flow control packets. If this pin is configured to low state the switch will execute symmetrical PAUSE operation as defined in 802.3x. The function of enabling/disabling the flow control in the EEPROM is now available on a per port basis rather than setting flow control globally for all ports and separate enabling/disabling flow control ability can be performed on either receive or transmit side of a port. TC9204M can be instructed to ignore the auto-negotiation result for full duplex flow control ability. When the FrcFdFC shared configuration pin or the equvalent register in the EEPROM is equal to 1, the link partner will be considered to have full duplex flow control capable no matter of auto-negotiation result. The FrcFdFC setting is effective only for ports configured in 10/100 Mbps speed modes. When the FrcGbFC and the equivalent register in the EEPROM is equal to 1, the link partner will be considered symmetrically and asymmetrically towards link partner full duplex flow control capable no matter of auto-negotiation result. The FrcGbFC setting is effective only for ports configured in 1000 Mbps speed mode. The TC9204M executes backpressure algorithm for half duplex flow control, supporting both collision-based and carrier-based backpressure. For collision-based backpressure the switch will be forced to send collision signals to the terminal that sends packets to TC9204M. While TC9204M detects an incoming frame that it wishes to backpressure with carrier sense signals, the switch will start transmission to that port. If no packet is available at that moment for transmission then the MAC layer will generate short jamming frames. Additionally, an aggressive backoff will be executed by the transmit MAC after each of the forced collisions. The transmit MAC will chose between 0 and 1 slot times to backoff. This will grant a fast recovery for the switch's congested port and will secure the channel for the congested port in case it wishes to transmit (empty its buffers). If desired, the backoff can be completely
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disabled using shared configuration pin DisBPBk or EEPROM. In this case the switch will start transmitting with minimum IFG after carrier sense is deasserted and followed after collision. For carrier-based backpressure the switch will use the deferral mechanism rather than the collision backoff mechanism. The transmit MAC will jam the line by sending continuous preamble. The link partner will see the channel busy and thus it will defer transmission without imposing any additional backoff delay. The jamming procedure will have short break to avoid jabber condition and the break will also be short enough to prevent the other stations from starting transmission. Preamble can be sent this way as long as necessary. If valid packets became available for transmission during this period then jamming will be interrupted and the packets will be transmitted with standard IFG (Inter-Frame Gap). In this case backpressure is executed the same way as collision based mechanism. Carrier based backpressure can be selected using shared configuration pin CrBP or EEPROM. Backpressure operation can be disabled globally using the shared configuration pin DisBkPr or per port basis using the EEPROM. By default forward pressure is also enabled whenever backpressure is enabled. Forward pressure is executed only in extreme congestion conditions that normally do not occur often. This flow control procedure is highly efficient in minimizing the packet loss. If desired, the forward pressure can be disabled by the EEPROM setting. If a HUB is connected to many workstations, one of the ports may be partitioned in heavy traffic when the switch executes backpressure. TC9204M can prevent this by discontinuing the backpressure process after a predefined number of consecutive collisions have reached. This function can be enabled using the shared configuration pin FullBP or adjusting EEPROM setting. Unlike other settings, to enable this feature the pin/bit should be set to '0'. The respective number of collisions defaults to 28 and can be specified using the EEPROM. In addition, when this feature is enabled the MAC will either grant receiving the next packet without colliding it, after which, it will resume the backpressure, or will completely quit backpressure waiting for a new XOFF command from internal flow control management device.
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7 Broadcast Throttling
In case of excessive broadcast, TC9204M will throttle the broadcast traffic based on buffer memory loading. Both global buffer pool loading and source port loading are considered. The number of frame buffers that can be consumed by broadcast packets received from an individual source port is permanently limited to the EEPROM configurable value (contained by SrcLoadTrsh field from Broadcast Configuration Register). The default value is 32 when the EEPROM is not present. Additionally, regarding the global aspect, broadcast frames are always dropped by broadcast queues overflow. Two broadcast queues are implemented within TC9204M, one for low and normal priority (Classes 0 and 1) and another for higher priorities (Classes 2 and 3). Both filtering mechanisms described above can be avoided by enabling the flow control for broadcast process. This mechanism can be enabled using the FcBcstEn pin shared configuration or by adjusting the EEPROM setting. In this case the loading thresholds will never be reached and as result no broadcast packet will be dropped although the filtering mechanism always remains active. If the broadcast flow control is disabled TC9204M is still capable of taking continuous broadcast frames from one port and deliver them to all the other ports at maximum speed without losing packets. Independent of the throttling mechanisms, a bandwidth based broadcast throttling can be enabled using the BcstThrot pin or by EEPROM setting. When this process is active, the receive broadcast bandwidth per port will be limited to a value between 1% and 31% from the port's maximum bandwidth. This percentage is encoded within ThrotTrsh field from EEPROM's Broadcast Configuration Register. Default value is 5 (%). Whenever the broadcast traffic bandwidth exceeds the above limit some broadcast frames will be randomly dropped in order to precisely meet the enforced bandwidth. TC9204M has the ability to give an indication about its status, from the broadcast packets handling issue perspective. Its BcstLED pin can signal either if the incoming broadcast packets are dropped or if broadcast packets overflow a certain threshold. During reset, this pin has the meaning of BcstCfg shared configuration pin. If this pin is sampled low at reset, the BcstLED will behave as a broadcast packets dropping indicator, it lights periodically whenever a broadcast packet is dropped due to buffer overflow. If this pin is sampled high at reset, the led will light periodically whenever the percentage of the received broadcast packets bandwidth in the last second to the whole port bandwidth exceeds a certain threshold specified in the EEPROM. The default value for this threshold is 40% from the whole bandwidth per port.
8
Port Mirroring
Although TC9204M is a smart switch, it has the ability to set a pair of mirroring ports. This feature is available only through EEPROM settings. The port mirroring feature can be enabled by setting a value of `1' in either EnTxMirror field from EEPROM's PortMirrorConfig register or EnRxMirror field from the same register, or both. When port-mirroring feature has been enabled, the SourcePort field from EEPROM's PortMirrorConfig register selects the monitored port while DestinationPort field from EEPROM's PortMirrorConfig register selects the monitoring port. The traffic on the monitored (mirror source) port will be forwarded to the monitor port (mirror destination). Both ports can be any of the TC9204M's ports. If EnRxMirror field is set to `1' then all the incoming traffic of the mirror source port will be simultaneously forwarded towards its due destination and to the monitoring port. The bad CRC / undersized frames will be filtered out. If EnTxMirror field is set to `1' then all the outgoing traffic of the mirror source port will be also forwarded to the monitoring port.
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9 Physical Layer Configuration / Polling
TC9204M embeds a Physical Layer MII Management configuration / polling entity which provides speed, duplex, link status and link partner full duplex flow control ability information to the switch. This information is obtained by continuously polling the status of Physical Layer devices through the serial management interface. The entity is under control of EEPROM settings and it can operate in four different modes. The polling entity also performs Phy configuration procedure at two seconds after reset and each time EEPROM control information changes. The following operating modes are available per port basis (selectable by ANMode field from EEPROM's ConfigRegP[x]): 00 - Normal Mode (assumed by default when EEPROM is not present): In this mode the Auto-Negotiation Enable bit from MII Control Register (0.12) is checked first. If it is found enabled then TC9204M will disable advertisement for 1000BASE-T half duplex technology (9.8) and will advertise the full duplex flow control ability (4.10:11) according with internal flow control enable settings. Auto-negotiation is restarted leaving unchanged the rest of technology advertisements. Then Auto-Negotiation Advertisement register (4), Link Partner Base Page Ability register (5) and GMII registers (9:10) are polled continuously at 2 seconds interval in order to execute highest common denominator resolution. If auto-negotiation is disabled as reported by 0.12 then the switch will configure itself using bits 0.13 and 0.8 of Control register, and will consider link partner full duplex flow control capable. Gigabit speed will be disabled. 01 - Advertise one mode: Auto-Negotiation Enable is checked and if found to be disabled TC9204M will attempt to enable it. If successful the switch will force the port's speed and duplex mode by advertising only the technology corresponding to the Speed and Duplex fields from EEPROM's ConfigRegP[x], otherwise bits 0.8 and 0.13 will be read for configuration and gigabit speed will be disabled. Full duplex flow control ability is also advertised along with selected technology and then auto-negotiation is restarted. An auto-negotiation register polling is executed as in Normal Mode. 10 - Advertise multiple modes: This mode is similar with previous one except that it advertises the technology corresponding to the forced mode and all lower position technologies, down to 10BASE-T half duplex. 11 - Disable Auto-Negotiation: When this mode is selected then auto-negotiation is disabled by setting bit 0.12 to `0' and the forced speed and duplex mode will be written to Configuration Register, bits 0.13, 0.6 and 0.8. This mode is available only for 10/100 Mbps speed modes so bit 0.6 will always be written as `0'. Link partner will be considered full duplex flow control capable. In addition to the force mode feature, the TC9204M internal speed and duplex can be chosen between enforced ones (Speed and Duplex fields from EEPROM's ConfigRegP[x]) and polling results by means of ForceIntMode configuration. Independently of Phy configuration/polling operation mode the Link Status is also permanently monitored. If a Physical device reports link failure via 1.2 status bit then TC9204M disables transmission on associated port without holding any memory resources allocated for its transmission queues. The reported Link Status can be forced to `1' using ForceLink bit from the same ConfigRegP[x] register.
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10 EEPROM Interface
TC9204M can be configured using a serial EEPROM device type AT24C02A (2048 bits organized as 208 pages of 1 byte each). With this device the manufacturer can deliver a pre-configured system to their customers while the customers can reconfigure the system and retain their preferences. TC9204M also provides a virtual internal EEPROM mode, which enables the programming entity to write the configuration data directly into the chip, without using the external EEPROM. In this mode the configuration data is lost after reset procedures. The TC9204M is able to operate without this device and can make effective use of its features using only the pin configuration interface. The EEPROM configuration provides additional features and it can override all pin interface settings offering a jumperless configuration mode. For this reason equivalent EEPROM settings can be found for every configuration pin. A validation bit is provided for each one of the EEPROM Configuration Registers. A dedicated Validation Register is reserved for this purpose and corresponding bits from this register must be set in order to enable the desired EEPROM configurations. The EEPROM configuration information is accessed by the TC9204M after each reset procedure.
10.1
Reprogramming the EEPROM for reconfiguration
If the `Reset' pin is hold Low the TC9204M`s EEPROM interface will go into high impedance state. This feature enables easy reprogramming of the EEPROM during installation or reconfiguration. The EEPROM can be reprogrammed using an external parallel port. A dedicated signal from this port can be used to hold the RESET pin Low. Once the TC9204M interface pins have got to the high impedance state the EEPROM can be programmed by the parallel port trough the SDA and SCL pins. To enable the AT24C02A device to be accessed by the TC9204M its page address input pins must be hardwired to `0'. For virtual EEPROM mode the programming can be done using the same AT24C02A byte write protocol but page address bits must be "100" (A2 downto A0).
SDA
TC9204M
SCL
EEPROM
Reset
Parallel Port
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10.2 EEPROM Address Map
Bits [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] Register Name ValidReg [ 7 downto 0 ] ValidReg [ 15 downto 8 ] ValidReg [ 23 downto 16 ] ValidReg [ 24 downto 31 ] ValidReg [ 32 downto 39 ] ConfigRegP0 [ 7 downto 0 ] ConfigRegP0 [ 15 downto 8 ] Validation Bit ConfigRegP0 DESCRIPTION Validation Register Validation Register Validation Register Validation Register Validation Register Port 0 Configuration Register Physical Address EEPROM 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h - 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 20h 21h - 2dh 2eh 2fh 30h 31h 32h 33h 34h 35h 36h 37h
ConfigRegP2 [ 7 downto 0 ] ConfigRegP2 [ 15 downto 8 ]
ConfigRegP2
Port 2 Configuration Register
ConfigRegP4 [ 7 downto 0 ] ConfigRegP4 [ 15 downto 8 ]
ConfigRegP4
Port 4 Configuration Register
ConfigRegP6 [ 7 downto 0 ] ConfigRegP6 [ 15 downto 8 ]
ConfigRegP6
Port 6 Configuration Register
IFGConfigP0 [7 downto 0] IFGConfigP2 [7 downto 0] IFGConfigP4 [7 downto 0] IFGConfigP6 [7 downto 0]
Reserved IFGConfigP0 IFGConfigP2 IFGConfigP4 IFGConfigP6 Reserved FlowContrReg
Port 0 IFG Configuration Port 2 IFG Configuration Port 4 IFG Configuration Port 6 IFG Configuration
FlowControlReg [7 downto 0] Flow Control Register FlowControlReg [15 downto 8] BPTimeValue [7 downto 0] BPTimeValue Backpressure Time Value Register BPTimeValue [15 downto 8] FCBaseAddress [47 downto 40] FCBaseAddress Flow Control Source Base Address Register FCBaseAddress [39 downto 32] FCBaseAddress [31 downto 24] FCBaseAddress [23 downto 16] FCBaseAddress [15 downto 8] FCBaseAddress [7 downto 0]
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Preliminary Data Sheet
Physical Address EEPROM 38h - 3bh 3ch 3dh 3eh 3fh 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4ah 4bh - 4eh 4fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5ah 5bh 5ch 5dh 5eh 5fh - 6fh 70h 71h 72h 73h 74h 75h 76h Bits Register Name Validation Bit Reserved [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] BroadcastConfig [ 7 downto 0 ] BroadcastConfig [15 downto 8 ] IPTosMapping [ 7 downto 0 ] IPTosMapping [15 downto 8 ] VLANPriMapping [7 downto 0 ] VLANPriMapping [15 downto 8 ] CoSBandwidth [7 downto 0 ] CoSBandwidth [15 downto 8 ] [7 downto 0 ] [15 downto 8 ] CosConfig [7 downto 0] PortMirrorReg [7 downto 0 ] PortMirrorReg [15 downto 8 ] GeneralConfig [ 7 downto 0 ] PortVLANEn VLAN0Reg [ 7 downto 0] VLAN1Reg [ 7 downto 0] VLAN2Reg [ 7 downto 0] VLAN3Reg [ 7 downto 0] VLAN4Reg [ 7 downto 0] VLAN5Reg [ 7 downto 0] VLAN6Reg [ 7 downto 0] VLAN7Reg [ 7 downto 0] DataWriteReg [15 downto 8 ] DataWriteReg [ 7 downto 0 ] PhyAddress [ 7 downto 0 ] RegAddress [ 7 downto 0 ] IOControl [ 7 downto 0 ] DataReadReg [ 7 downto 0 ] DataReadReg [ 15 downto 8 ] BroadcastConfig Broadcast Configuration Register IPTosMapping IP Priority Mapping Register DESCRIPTION
VLANPriMapping VLAN Priority Mapping Register CoSBandwidth CoS Bandwidth Register Reserved Register CoSConfig PortMirrorReg GeneralConfig Reserved PortVLANEn PVIDEn Reserved PVIDEn Reserved PVIDEn Reserved PVIDEn Reserved PVIDEn Reserved PVIDEn Reserved PVIDEn Reserved PVIDEn Reserved CoS Configuration Register Port Mirroring Configuration Register General Configuration Register Port VLAN Enable Register ID 0 virtual LAN Register ID 1 virtual LAN Register ID 2 virtual LAN Register ID 3 virtual LAN Register ID 4 virtual LAN Register ID 5 virtual LAN Register ID 6 virtual LAN Register ID 7 virtual LAN Register Data Write Register Phy Address Register Phy's Register Address Register IO Control Register Data Read Register
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Preliminary Data Sheet
10.3
10.3.1
Register Description
Validation Register
- Address: 00h - 04h
39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ValidationReg
ConfigRegP0 Reserved ConfigRegP2 Reserved ConfigRegP4 Reserved ConfigRegP6 Reserved not used IFGConfigP0 Reserved IFGConfigP2 Reserved IFGConfigP4 Reserved IFGConfigP6 Reserved not used FlowContrReg BPTimeValue Reserved BroadcastConfig IPTosMapping VLANPriMapping QoSBandwidth Reserved QoSConfig PortMirrorReg GeneralConfig not used PortVLANEn not used
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Bit(s) 39 - 0 Field ValidationReg Description EEPROM's Configuration Registers Validation Register - each bit from this register corresponds to an EEPROM Configuration Register. To enable the use of a certain configuration register, a value of `1' shall be written to its corresponding bit from the validation register. - validation bit for Port 0 Configuration Register - should be `0' - validation bit for Port 2 Configuration Register - should be `0' - validation bit for Port 4 Configuration Register - should be `0' - validation bit for Port 6 Configuration Register - should be `0' - validation bit for Port 0 IFG Configuration Register - should be `0' - validation bit for Port 2 IFG Configuration Register - should be `0' - validation bit for Port 4 IFG Configuration Register - should be `0' - validation bit for Port 6 IFG Configuration Register - should be `0' - validation bit for Flow Control Register - validation bit for Back Pressure Time Value Register - Reserved Register - validation bit for Broadcast Configuration Register - validation bit for IP Priority Mapping Register - validation bit for VLAN Priority Mapping Register - validation bit for CoS Bandwidth Register - Reserved Register - validation bit for CoS Configuration Register - validation bit for Port Mirroring Register - validation bit for General Configuration Register - validation bit for Port VLAN Enable Register
ValidationReg ConfigRegP0 Reserved ConfigRegP2 Reserved ConfigRegP4 Reserved ConfigRegP6 Reserved IFGConfigP0 Reserved IFGConfigP2 Reserved IFGConfigP4 Reserved IFGConfigP6 Reserved FlowContrReg BPTimeValue TrunkConfig BroadcastConfig IPTosMapping VLANPriMapping CoSBandwidth Reserved CoSConfig PortMirrorReg GeneralConfig PortVLANEn
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10.3.2 Port [X] Configuration Register
- Addresses: 05h - 14h - Note: x is in range 0 to 7
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ConfigRegP[x]
ANMode ForceIntMode Speed Duplex ForceLink not used TxDisable RxDisable DisFdxFCTx DisFdxFCRx DisBackPres PortPriorityEn PortPriority
Bit(s) 1-0 2 4-3 5 6 7 8 9 10 11 12 13 15 - 14 ANMode
Field ANMode ForceIntMode Speed Duplex ForceLnk not used TxDisable RxDisable DisFdxFCTx DisFdxFCRx DisBackPres PortPriorityEn PortPriority
Description Operating mode selection for the phy configuration/polling entity Internal speed and duplex selection enforcement Internal speed selection (10 Mbps/100Mbps/1000Mbps) Internal duplex selection (full/half) Force Link Status to `ON' not used Disable transmit MAC Disable receive MAC Disable flow control in full duplex on transmit side Disable flow control in full duplex on receive side Disable backpressure Enable port priority Sets the priority class(class 0, class 1, class 2, class 3)
This field selects the way auto-negotiation advertisements are configured by the TC9204M's physical layer management polling entity and the way Phy speed and duplex modes are extracted from management registers. It can enable EEPROM forced modes that also use Duplex and Speed bits below to configure the Phy mode. 00 - Normal Mode 01 - Advertise one mode 10 - Advertise multiple modes 11 - Disable auto-negotiation Default is "00"(0). This bit selects the source of internal port mode configuration. When this bit is `0' the port's speed and duplex is configured according to Phy polling results, otherwise it is set as indicated by following Speed and Duplex. Default is `0'.
ForceIntMode
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Speed Used by the physical layer management polling entity to configure physical layer's speed mode when EEPROM forced modes are selected. Additionally this bit can be used to directly force the internal speed mode. 00 - 10M 01 - 100M 10 - 1000M Used by the physical layer management polling entity to configure physical layer's duplex mode when EEPROM forced modes are selected. Additionally this bit can be used to directly force the internal duplex mode. Setting this bit to '1' will force the internal polled link status of the corresponding port to "ON". Default is `0'. Setting this bit to '1' will disable the transmission MAC device, thus inhibiting transmission on the corresponding port. Default is `0'. Setting this bit to '1' will disable the receiving MAC device, thus inhibiting receiving on the corresponding port. Default is `0'. Setting this bit to '1' will disable flow control operation for full duplex mode on transmit side (transmission of pause frames). Default is `0'. Setting this bit to '1' will disable flow control operation for full duplex mode on receive side (pausing frame transmission). Default is `0'. Setting this bit to '1' will disable flow control for half duplex mode (backpressure). Default value is its corresponding DisBkPr pin value. Setting this bit to '1' will force the corresponding port to the priority set within the PortPriority field, otherwise the pin configuration will be used. This bit will set one of the four priority classes on the corresponding port.
Duplex
ForceLnk TxDisable RxDisable DisFdxFCTx DisFdxFCRx DisBackPres PortPriorityEn PortPriority
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10.3.3 Port [X] IFG Configuration Register
- Addresses: 19h - 20h
76543210
IFGConfigP[x]
IFGConfig RedGbBndw GbBndwSel not used
Bit(s) 3-0 4 6-5 7 IFGConfig
Field IFGConfig RedGbBndw GbBndwSel not used
Description Interframe Gap Configuration Reduced gigabit bandwidth Gigabit bandwidth selection not used
These bits are used to set the minimum IFG with 32-bit time resolution. The default matches the standard minimum IFG of 96-bit time: `0011' (3). IFGConfig 0001 0010 0011 0100 ... 1111 0000 IFG (bit time) 32 64 96 (default) 128 ... 480 512
RedGbBndw
Setting this bit to '1', will enable a 1000Mbps port to reduce its transmission bandwidth to the percentage indicated by the GbBndwSel field. Setting this bit to `0', the GbBndwSel field will be meaningless and the port will make use of its full transmission bandwidth. This bit is in effect only when the port's speed mode is 1000Mbps. Default is `0'. Transmission bandwidth enforcement when in 1000 Mbps mode. GbBndwSel 00 01 10 11 Transmission bandwidth 50% 66% 80% 90%
GbBndwSel
This feature can be used to avoid congestion in some LAN nodes without flow control capabilities or to avoid server overloads
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10.3.4 Flow Control Register
- Address: 2Eh, 2Fh
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FlowControlReg
FullBP BPMaxCol BPSkip1 CarrBP DisFwPres DisBPBk FrcFdxFC FrcFdxFCGb DirFCAdr not used
Bit(s) 0 6-1 7 8 9 10 11 12 13 15 - 14 FullBP
Field FullBP BPMaxCol BPSkip1 CarrBp DisFwPres DisBPBk FrcFdxFC FrcFdxFCGb DirFCAdr not used
Description Full backpressure Maximum number of collisions for backpressure Skip one packet for backpressure operation Carrier backpressure Disable forwardpresure Disable backoff during backpressure Force full duplex flow control in 10/100 Mbps Force full duplex flow control in 1000 Mbps Direct flow control addressing not used
In normal operation the backpressure process is executed until flow control condition disappears or until the time limit for backpressure is reached. This limit is based on EEPROM's BPTimeValue register. When this configuration is `0' the backpressure process will be also limited from exceeding the value contained in BPMaxCol field. Default value is its corresponding FullBP pin value. Specifies the number of consecutive collisions that will determine TC9204M to quit backpressure (see the setting above). Default is `011100' (28). If FullBP setting is configured to `0' and a number of BPMaxCol collisions is reached, the MAC will ensure receiving the next packet without colliding it if this bit is set to `1', after which will resume the backpressure. Otherwise it will completely quit backpressure waiting for a new XOFF command from internal flow control entity. Default is `0'. Setting this bit to `1' will enable carrier-based backpressure, otherwise only collision-based backpressure is executed. Default value is its corresponding CarrBp pin value.
BPMaxCol BPSkip1
CarrBp
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DisFwPres Whenever backpressure is enabled, in case of extreme congestion (memory overload) forward pressure is also executed unless deactivated by this bit. Forward pressure is never executed when backpressure is disabled. Setting this bit to `1' will disable forward pressure for all half duplex ports. Default is `0'. Setting this bit to `1' will cause no backoff to be executed when a half duplex port is in backpressure mode. This means a new collision can be forced immediately after the previous one if carrier sense is observed. Setting this bit to `0' will enable a very aggressive backoff to be executed (recommended). Default value is its corresponding DisBPBk pin value. Setting this bit to `1' will instruct TC9204M to disregard the auto-negotiation result for the full duplex flow control ability. Link partner will be considered full duplex flow control able. This setting is effective only for ports configured in 10/100 Mbps speed modes. Default is `0'. Setting this bit to `1' will instruct TC9204M to disregard the auto-negotiation result for the full duplex flow control ability. Link partner will be considered able to execute symmetric and asymmetric towards link partner full duplex flow control. This setting is effective only for ports configured in 1000 Mbps speed mode. Default is `0'. Setting this bit to `1' will enable direct flow control addressing mechanism, otherwise direct flow control addressing is disabled. Default is `0'.
DisBPBk
FrcFdxFC
FrcFdxFCGb
DirFCAdr
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10.3.5 Backpressure Time Value Register
- Address: 31h, 30h
15 14 13 12 11 10 9 8
76543210
31h
BPTimeValue
30h
BPTimeValue
Bit(s) 15 - 0
Field BPTimeValue
Description Backpressure time value
BPTimeValue
A 16 bit value used to compute internal time value for backpressure operation. Default value is `0000100000000000'(2048).
10.3.6
Flow Control Port Base Address Register
- Address: 32h, 33h, 34h, 35h, 36h, 37h
47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FCBaseAddress
FCBaseAddress
Bit(s) 47 - 0
Field FCBaseAddress
Description Source port base address for flow control packets
FCBaseAddress
Contains a 48-bit MAC address used to generate the individual port address used in direct flow control addressing. The port addresses are obtained by incrementing this base address and assigning the result to the TC9204M's ports starting with port 0. The least significant 5 bits of this address will be ignored and replaced with `0', so these bits will encode the port number in the actual port address.
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10.3.7 Broadcast Configuration Register
- Address: 3Dh, 3Eh
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BroadcastConfig
SrcLoadTrsh FCBcstEn FCBcstMode not used ThrotTrsh BcstThrot Reserved not used
Bit(s) 4-0 5 6 7 11 -8 12 14 - 13 15
Field SrcLoadTrsh FCBcstEn FCBcstMode not used ThrotTrsh BcstThrot Reserved not used
Description Source port loading limit for broadcast Flow control broadcast enable Flow control broadcast mode not used Global buffer pool loading threshold for broadcast Broadcast throttling (bandwidth) not used
SrcLoadTrsh FCBcstEn
The maximum number of frame buffers used on each receiving port for broadcast. Default is `11000' (24). Setting this bit to `1' will enable flow control mechanism for broadcast frames. Setting this bit to `0' will cause broadcast packets to be dropped on queue overflow condition. Default value is its corresponding FcBcstEn pin value. This bit selects the source of flow control for broadcast operation: `0' - broadcast flow control is issued on source port basis `1' - broadcast flow control is issued by any of the two broadcast queues Default value is its corresponding FcBcstMode pin value. Setting this bit to `1' will enable bandwidth based broadcast throttling. The value represents the maximum percentage of the full receiving bandwidth than can be used for broadcast. Default is `00101'(5%). Setting this bit to `1' will enable throttling for broadcast frames. Default value is its corresponding BcstThrot pin value.
FCBcstMode
ThrotTrsh
BcstThrot
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10.3.8 IP Priority Mapping Register
- Address: 3Fh, 40h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IPTosMapping
Tos0Class Tos1Class Tos2Class Tos3Class Tos4Class Tos5Class Tos6Class Tos7Class
Bit(s) 1-0 3-2 5-4 7-6 9-8 11 - 10 13 - 12 15 - 14
Field Tos0Class Tos1Class Tos2Class Tos3Class Tos4Class Tos5Class Tos6Class Tos7Class
Description priority mapping for IP precedence 0 priority mapping for IP precedence 1 priority mapping for IP precedence 2 priority mapping for IP precedence 3 priority mapping for IP precedence 4 priority mapping for IP precedence 5 priority mapping for IP precedence 6 priority mapping for IP precedence 7
Tos[x]Class
This field maps the IP priority level x found in the incoming frame to one of the four priority classes. The table bellow shows the mapping. Tos[x]Class 00 01 10 11 x ranges in the field 0 to 7. CoS Class 0 priority Class 1 priority Class 2 priority Class 3 priority
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10.3.9 VLAN Priority Mapping Register
- Address: 41h, 42h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VLANPriMapping
Pri0Class Pri1Class Pri2Class Pri3Class Pri4Class Pri5Class Pri6Class Pri7Class
Bit(s) 1-0 3-2 5-4 7-6 9-8 11 - 10 13 - 12 15 - 14 Pri[x]Class
Field Pri0Class Pri1Class Pri2Class Pri3Class Pri4Class Pri5Class Pri6Class Pri7Class
Description priority mapping for VLAN user_priority 0 priority mapping for VLAN user_priority 1 priority mapping for VLAN user_priority 2 priority mapping for VLAN user_priority 3 priority mapping for VLAN user_priority 4 priority mapping for VLAN user_priority 5 priority mapping for VLAN user_priority 6 priority mapping for VLAN user_priority 7
This field maps the VLAN priority level x found in the incoming frame to one of the four priority classes. The table bellow shows the mapping. Pri[x]Class 00 01 10 11 x ranges in the field 0 to 7. CoS Class 0 priority Class 1 priority Class 2 priority Class 3 priority
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10.3.10 CoS Bandwidth Register
- Address: 43h, 44h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CoSBandwidth
Cos0Weight not used Cos1Weight not used Cos2Weight not used Cos3Weight not used
Bit(s) 2-0 3 6-4 7 10 - 8 11 14 - 12 15
Field CoS0Weight not used CoS1Weight not used CoS2Weight not used CoS3Weight not used
Description 000 not used The weight for priority class 1 queue not used The weight for priority class 2 queue not used The weight for priority class 3 queue not used
CoS[y]Weight
This field sets the weight for its associated priority queue. The transmission bandwidth percentage given to the associated queue is set by the formula below:
3
Queue y's priority [%] = F(CoS[y]Weight) * 100 / ( F(CoS[n]Weight) )
n=0
Note: y ranges in 0 to 3 and F is a tabled function described bellow: f("000") = 1 f("001") = 2 f("010") = 4 f("011") = 8 f("100") = 16 f("101") = 32 f("110") = not used f("111") = not used
10.3.11
Reserved Register
- Address: 45h, 46h
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10.3.12 CoS Configuration Register
- Address: 47h
76543210
CosConfig
EnIPPr EnVLANPr CosResolution VLANPrec DefCoS not used
Bit(s) 0 1 2 3 5-4 7-6 EnIPPr
Field EnIPPr EnVLANPr CoSResolution VLANPrec DefCoS not used
Description Enable IP priority Enable VLAN priority CoS Resolution Mode VLAN Precedence Default Class of Service not used
Setting this field to `1' will enable IP prioritization. CoS resolution function will consider TOS Precedence bits from IP Header. Default value is its corresponding EnIPPr pin value. Setting this field to `1' will enable VLAN prioritization. CoS resolution function will consider user-priority bits (TCI field) from 802.1Q VLAN Tag Header. Default value is its corresponding EnVLANPr pin value. When this bit is set to `0' the CoS resolution function will assign to each frame the highest CoS obtained from all enabled prioritization sources. Setting this field to `1', the resolution function will perform a prioritized parsing of CoS sources, depending of VLANPrec bit. The CoS will be assigned considering the first source that has been found within the frame (VLAN or IP). If none of the VLAN or IP prioritization sources have been found then the port based prioritization is considered if enabled, otherwise the frame will be assigned the default CoS. Default is `1'. If CoSResolution field is set to `0', this field is meaningless. When CoSResolution field is set to `1', this field will set the prioritization sources precedence for the resolution function. A value of `1' will set the following precedence (from highest to lowest): VLAN priority, IP priority, port priority. A value of `0' will set the following precedence (from highest to lowest): IP priority, VLAN priority, port priority. Default is `0'. This is the CoS a frame will receive when port based prioritization is disabled and both VLAN and IP headers are not found (or the corresponding VLAN / IP prioritizations are also disabled). This configuration can be used especially when CoSResolution setting is `0'. Default is "01" (CoS 1).
EnVLANPr
CoSResolution
VLANPrec
DefCoS
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10.3.13 Port Mirroring Register
- Address: 48h, 49h
15 14 13 12 11 10 9 8 76543210
PortMirrorReg
Source Port not used Destination port not used EnRxMirror EnTxMirror not used not used not used
Bit(s) 2-0 3 6-4 7 8 9 10 11 15 - 12
Field SourcePort not used DestinationPort not used EnRxMirror EnTxMirror not used not used not used
Description Source port(monitored port) not used Destination port(monitoring port) not used Enable mirroring on receiving packets Enable mirroring on transmitting packets not used not used not used
SourcePort
One of the eight ports of the switch that is intended for been monitored through port mirroring feature. If enabled, the traffic on this port can be additionally forwarded to the monitoring port. Only one port can be monitored at a time. One of the eight ports address's of the switch that is intended to monitor one of the other ports through port mirroring feature. This port will receive all traffic on the mirror source port. Setting this bit to `1', the destination port will mirror all the source port's incoming traffic. Setting this bit to `1', the destination port will mirror all the source port's outgoing traffic.
DestinationPort
EnRxMirror EnTxMirror
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10.3.14 General Configuration Register
- Address: 4ah
7 6 5 4 3 2 1 0
G en eralC o n fig
AgeT imeR eg D isA ging F wdBadC R C F wdU ndersize R ejM C T R ejR D A not used
Bit(s) 1-0 2 3 4 5 6 7
Field AgeTimeReg DisAging FwdBadCRC FwdUndersize RejMCT RejRDA not used
Description Sets the aging time Disable aging Forward bad CRC packets Forward undersized packets Reject MAC Control Type frames Reject 802.1D Reserved Group Addresses DA frames not used
AgeTimeReg
Allows 4 values for the aging time to be chosen from. 00 - 300 seconds 01 - 600 seconds 10 - 900 seconds 11 - 1200 seconds Default is `01'(600 seconds). Setting this bit to '1' will cause TC9204M to disable its aging mechanism for the stored MAC addresses. Default is '0'. Setting this bit to `1' will enable forwarding of bad CRC packets. Default is '0'. Setting this bit to `1' will enable forwarding of undersized packets. Default is '0' Setting this bit to `1' will configure the switch to filter all frames with MAC Control Type (type 8808). Default is `0'. Setting this bit to `1' will configure the switch to filter all frames with 802.1D Reserved Group Destination Address except for Bridge Group Address (01-80-C2-00-00-00). Default value is its corresponding RejRDA pin value.
DisAging FwdBadCRC FwdUndersize RejMCT RejRDA
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10.3.15 Port VLAN Enable Register
- Address: 4fh
7 6 5 4 3 2 1 0
P o rtV L A N E n
VLAN0 VLAN1 VLAN2 VLAN3
Bit(s) 0 1 2 3 VLAN[y]
Field VLAN0 VLAN1 VLAN2 VLAN3
Description VLAN 0 enable VLAN 1 enable VLAN 2 enable VLAN 3 enable Enables/disables VLAN y. (y is in range 0 to 3)
10.3.16
VLAN [Y] Register
- Address: 50h, 52h, 54h, 56h, 58h, 5ah, 5ch, 5eh
7 6 5 4 3 2 1 0
V L A N [y ]R e g
P o rt0 N /A P o rt2 N /A P o rt4 N /A P o rt6 N /A
Bit(s) 0 1 2 3 4 5 6 7 Port[x]
Field Port0 N/A Port2 N/A Port4 N/A Port6 N/A
Description Port 0 membership to VLAN y Port 2 membership to VLAN y Port 4 membership to VLAN y Port 6 membership to VLAN y
Port x membership to VLAN y. `0' - Port x is not a member of VLAN y `1' - Port x is a member of VLAN y
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Preliminary Data Sheet
10.4 Writing / Reading PHY management registers via EEPROM interface
The following set of registers allows read/write operations through MDIO interface for direct managing of physical layer devices. This feature is available through virtual EEPROM mode. 10.4.1 Data Write Register
- Address: 70h, 71h
15 14 13 12 11 10 9 8
76543210
DataWriteReg
DataW riteReg
Bit(s) 15 - 0
Field DataWriteReg
Description MDIO Data Write Register
DataWriteReg
- Contains a 16 bit data word used to write a PHY management register.
10.4.2
Physical Layer Device Address Register
- Address: 72h
76543210
PhyAddress
DeviceAddress(4-0) not used
Bit(s) 4-0 7-5
Field DeviceAddress not used
Description Physical layer device address register not used
DeviceAddress
- Contains a 5 bit word used as device address in MDIO operations.
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10.4.3 Physical Layer's Register Address Register
- Address: 73h
76543210
RegAddress
RegAddress(4-0) not used
Bit(s) 4-0 7-5
Field RegAddress not used
Description Physical layer device's register address register not used
RegAddress
- Contains a 5 bit word used as register address in MDIO operations.
10.4.4
IO Status Control Register
- Address: 74h
76543210
IOControl
RnotW ValidDataRead MDIOError not used
Bit(s) 0 1 2 3-7 RnotW
Field RnotW ValidDataRead MDIOError not used
Description Operation code Valid Data Read MDIO Error not used
- Operation Code. Setting this bit to `1' will select read operation otherwise will select write operation. MDIO Read / Write operation is started by performing a virtual EEPROM write to IOControl register. - Indicates if DataReadReg register contains valid data. `1'- data valid `0'- read not performed yet - This bit signals errors on MDIO line. `1'- MDIO error. `0'- MDIO read successful.
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ValidDataRead
MDIOError
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Preliminary Data Sheet
10.4.5 Data Read Register
- Address: 76h, 75h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
76h
DataReadReg
75h
DataReadReg
Bit(s) 15 - 0
Field DataReadReg
Description MDIO Data Read Register
DataReadReg
- Contains a 16 bit data word read from a PHY management register.
Write Operation.
Before starting a write operation the following registers need to be set : PhyAddress - written with MDIO device address RegAddress - written with MDIO register address DataWriteReg - data word to be write to selected register The write operation is then started by performing a write to IOControl register with bit 0 cleared.
Read Operation.
Before starting a read operation the following registers need to be set : PhyAddress - written with MDIO device address RegAddress - written with MDIO register address The write operation is then started by performing a write to IOControl register with bit 0 set. Subsequently, the IOControl register needs to be monitored in order to detect MDIO operation error reported via IOControl's bit 2. The ValidDataRead bit is always read as `1' unless the EEPROM line is driven at over 1MHz speed. If no error occurred then data can be read from DataReadReg.
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11 Timing Requirements
11.1 GMII / MII Receive Timing Requirements
Symbol
Rx_Clk Rx_Clk
Description Receive clock period GMII Receive clock period MII RxDv, RxData to Rx_Clk rising setup time RxDv, RxData to Rx_Clk rising hold time
TRx_Clk
Min. 2 0.5
Typ. 8 40 -
Max. -
Unit ns ns ns ns
TsRx_Clk ThRx_Clk
Rx_Clk RxDv RxData TsRx_Clk ThRx_Clk
GMII / MII Receive
11.2
GMII / MII Transmit Timing
Symbol TTx_Clk TTx_Clk TdTx_Clk Description Transmit clock period GMII Transmit clock period MII Tx_En, TxData to Tx_Clk rising delay Min. 1 Typ. 8 40 Max. 4 Unit ns ns ns
TTx_Clk Tx_Clk Tx_En TxData
TdTx_Clk
GMII / MII Transmit
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TC9204M
Preliminary Data Sheet
11.3 PHY Management (MDIO) Timing
Symbol Tch Tcl Tcm Tmd Tmh Description MDCK High Time MDCK Low Time MDCK period MDIO output delay MDIO hold time Min. 10 Typ. 300 300 600 Max. 50 Unit ns ns ns ns ns
MDClk
Tms
Tmh
MDIO
MDIO Write Cicle
MDClk Tcl Tcm MDIO Tch Tmd
MDIO Read Cicle
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TC9204M
Preliminary Data Sheet
11.4 EEPROM Timing
Symbol fSCL tLOW tHIGH tBUF tHD.STA tSU.STA tHD.DAT tSU.DAT tSU.STO tAA tDH Description SCL frequency Clock Pulse Width Low Clock Pulse Width High Time the bus must be free before starting a new transmission Start Hold Time Start Setup Time Data Hold Time Data Setup Time Stop Set-up Time Clock Low to Data Out Valid Data Out Hold Time Min. 10 10 5 5 5 5 5 5 0 Typ. 66.6 Max. 4.9 Unit KHz us us us us us us us us us us
tLOW
tHIGH tSU.STO tBUF
SCL
tSU.STA tHD.STA tAA
VALID
tHD.DAT
VALID
SDA (output) SDA (input)
tSU.DAT
VALID
tDH
VALID
EEPROM Interface Timing
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Preliminary Data Sheet
12 Electrical Specifications
12.1 ABSOLUTE MAXIMUM RATINGS
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the Recommended Operating Conditions section. Exposure to the Absolute Maximum Conditions for extended periods may affect device reliability. PARAMETER Supply Voltage I/O Core Input Voltage Output Voltage Storage Temperature Operation Temperature Latch-up Current SYMBOL VDDI/O VDDCore VI VO TSTG TOPT ILATCH MIN. - 0.5 - 0.5 - 0.5 - 0.5 -65 0 >500 MAX. 4.6 2.5 6 6 +150 70 UNIT V V V V C C mA
Note: The maximum ratings are the limit value that must never be exceeded even for short time.
12.2
RECOMMENDED OPERATING CONDITIONS
The recommended operating conditions represents recommended values that assure normal logic operation. As long as the device is used within the recommended operating conditions, the electrical characteristics (DC and AC characteristics) are guaranteed. PARAMETER Supply Voltage I/O Core Junction Temperature Low-level input voltage High-level input voltage SYMBOL VDDI/O VDDCore Tj VIL VIH MIN. 3.0 1.95 -0.5 2.0 TYP. 3.3 2.0 MAX. 3.6 2.05 125 1.0 5.5 UNIT V V C V V
12.3
DC CHARACTERISTICS
SYMBOL VOL VOH IOL IOH VT VT+ VTII IOZ RPU RPD 56 51 MIN. 2.4 8.8 12.8 1.46 1.66 0.93 TYP. MAX. 0.4 17.0 40.0 1.76 1.79 1.06 +/-1000 +/-1000 122 127 UNIT V V mA mA V V V nA nA K K
PARAMETER Output low voltage Output high voltage Low level output current @VOL=0.4V High level output current @VOH=2.4V Input Treshold point GMII Input (Schmitt trig.) Low to High treshold point *1 GMII Input (Schmitt trig.) High to Low treshold point *1 Input leakage current (High and Low) Tri-state output leakage current (High and Low) Pull-up resistor Pull-down resistor Note: *1
14.1 25.7 1.60 1.75 1.01 +/-10 +/-10 77 69
This refers to all inputs described as GMII in the Pin Listing section.
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Confidential. Copyright (c) 2003, IC Plus Corp.
TC9204M
Preliminary Data Sheet
13 Package Detail
Lead pitch Package width x Package length Lead shape Sealing method 0.50 mm 28 x 28 mm Gullwing Plastic mold
IC Plus Corp.
Headquarters 10F, No.47, Lane 2, Kwang-Fu Road, Sec. 2, Hsin-Chu City, Taiwan 300, R.O.C. TEL : 886-3-575-0275 FAX : 886-3-575-0475 Website: www.icplus.com.tw Sales Office 4F, No. 106, Hsin-Tai-Wu Road, Sec.1, Hsi-Chih, Taipei Hsien, Taiwan 221, R.O.C. TEL : 886-2-2696-1669 FAX : 886-2-2696-2220
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